As technology nodes decrease, the density of features on a substrate increases. One way of increasing the density of features on the substrate is to form a three-dimensional integrated circuit (3DIC). However, 3DICs suffer from a problem of providing sufficient power integrity to each element of the 3DIC. Power integrity is a measure of stability of a power signal. The reduced area of the chip decreases the number of contact pads available to transmit power to components of the 3DIC. The fewer number of contact pads increases the resistance in the 3DIC. The increased resistance leads to greater concerns regarding power integrity. In some instances, a power spike or drop resulting from poor power integrity will cause the components of the 3DIC to function improperly.
Forming 3DICs also includes exerting force on the components of the 3DIC to form bonds between the components. In some instances, the forces exerted on the 3DIC components damages the components leading to improper functioning.
Some methods of testing 3DICs determine whether a 3DIC is functioning properly, but do not provide information regarding a reason for the failure, i.e., problems during manufacturing or poor power integrity. Some methods use an external scope to measure power integrity; however, these methods cannot measure power integrity during operation of the 3DIC. Some methods form a circuit to monitor power integrity during operation of the 3DIC, however, these circuits are complex and are designed specifically for each circuit, thus increasing production time and cost. These circuits also occupy significant area on the 3DIC, reducing the area available for other components.